Design and Implementation of High-Speed, Low Power Carry Look-Ahead Adder Using Hybrid GDI Logic and Transmission Gates

This paper presents a high-speed, low-power 4-bit Carry Look-Ahead Adder using a hybrid approach by integrating Gate Diffusion Input (GDI) logic and Transmission Gates (TG). The proposed design employs GDI logic to minimize transistor count and reduce power consumption in non-critical paths and ensure full voltage swing with low delay for critical carry propagation paths using TG. The hybrid CLA as compared to the traditional CMOS and fully GDI-based implementations shows major improvement in terms of power, delay, and area. It was synthesized and simulated using Cadence Virtuoso software at 90nm technology and the design resulted in the power reduction by 44.9%, delay by 38%, and area by 30% while maintaining functional reliability for different frequencies and loaded conditions. This novel hybrid CLA design is very appropriate for energy efficient and performance-driven applications in modern integrated circuits.