An Approach Towards Analysis of Leakage Energy in Digital Circuits Using Adiabatic Buffer

CMOS digital design faces significant challenges in integrating digital circuits due to physical limitations in accommodating complex logical systems within a single chip, requiring extensive optimization. The stacking of large elements within a single silicon wafer leads to signal and noise interferences. In existing systems, Adiabatic quantum flux parametron-based logic has been developed, where switching elements are largely partitioned within a single chip, with an emphasis on analysing leakage energy. In the proposed system, a combination of sequential circuits and a complex transfer system is considered, incorporating a complex added circuit. By comparing both circuits, the performance evaluation of the adiabatic quantum flux parametron circuit is analysed in terms of power efficiency. The simulation is implemented using QUARTUS II software to test the RTL flow.