High Performance Power Efficient Multiplier for AI Based Application

The investigations made on multipliers in this research has ended up in a novel multiplier design combining Vedic multiplication (8x8,16x16 and 64x64) with the Sklenksy adder to address challenges in modern digital systems, such as high power consumption, long latency, and large area. The Vedic multiplier reduces partial products through parallel computation, speeding up the multiplication process, while the Sklenksy adder optimizes carry propagation, enhancing overall speed. The design also integrates power suppression techniques to minimize spurious power dissipation, ensuring energy efficiency in high-speed operations. The proposed multiplier is evaluated based on key performance metrics: speed, power dissipation, and area. Comparisons with traditional multiplier designs show significant improvements in both speed, area and power efficiency. This optimized multiplier design is ideal for efficient, low-power applications in embedded systems, mobile devices and communication technologies, where balancing fast computation and minimal energy consumption is critical.