A New Ultra Low-Voltage Level Shifter Using Time-Borrowing Latch Technology and Integrated Re-Configurable Logic

As the level shifters has high demand while interconnecting sub-blocks under multiple power supply voltages, an efficient design of level shifter is required. This article proposes a unique level shifter design. Timing error prevention is the goal of using a time borrowing latch. This level shifter design can function at 0.3V, It has a very low voltage. A controlled cross-coupled pull-up network is utilised, enhancing speed and diminishing the circuit’s power usage. This proposed design is simulated using the Cadence Virtuoso EDA tool for 45nm technology. To achieve voltage level conversion from 0.3V to 1.8V, our level shifter has an average static power consumption of under 50 pW and an average propagation delay of 44 ns.