Implementation of Eavesdropping in CAN Network Using UVCs

The verification becomes more complex due to the complex ASIC designs. Verification team verifies the design using block level, chip level and system level testbench. So, the time required to achieve 100% code coverage and functional coverage takes more time when compared to design implementation. As per the ASIC design flow, the verification phase is followed by the design phase. In most semiconductors, verification and design implementation starts parallelly. After the implementation, the design is integrated in the verification testbench to capture verification and design bugs. The proposed method is to implement the UVC and to form a network by connecting the UVC’s in order to identify the verification bugs without integrating DUT. In this paper, CAN network is implemented and one of the major threats eavesdropping have been addressed. Identification of verification bug and bug fix time is eliminated by implementing this method which results in reduction of overall chip production time by 25%.