Evaluation of warpage tolerance of 100 μm dies to achieve void-free bond and 100% assembly yield
Bonding dies to wafers can lead to voiding and non-bonded areas due to warpage. In this work, the maximum die-level warpage required to achieve a fully bonded and void-free interface for a given dielectric stack is evaluated. 100 μm thick dies were prepared on a temporary carrier and bonded to a wafer using a ‘wafer-to-wafer’-like bonding flow, a collective die-to-wafer, and a direct die-to-wafer flow. The method used and the forces involved during bonding, primarily determine the tolerance of die-level warpage to achieve a void-free bond.
Authors
- B. Ralph Chou (ORCID: https://orcid.org/0000-0002-1374-0281)
- Dieter Cuypers (ORCID: https://orcid.org/0000-0003-0550-6273)
- Samuel Suhard
- Alain Phommahaxay
- Arnita Podpod
- Violeta Georgieva (ORCID: https://orcid.org/0000-0001-5770-1770)
- Filippo Ferraro (ORCID: https://orcid.org/0000-0002-9328-5548)
- Koen Kennes (ORCID: https://orcid.org/0000-0002-5987-2167)
- Andy Miller (ORCID: https://orcid.org/0000-0001-6103-1685)
- Joris Van Campenhout (ORCID: https://orcid.org/0000-0003-0778-2669)
- A.R. Patil
- Yoojin Ban (ORCID: https://orcid.org/0000-0001-7319-8132)
Institutions
- IMEC (BE)
Publication Details
- Published
- 2025-06-02
- DOI
- https://doi.org/10.1109/iitc66087.2025.11075472
- Citations
- 1
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.73