Electrical test demonstration for 0.55 NA EUV single patterning damascene process
This work presents the development of a single-layer damascene short loop process to evaluate the patterning performance of single-exposure 0.55 NA lithography. Electrical readouts of up to 3cm long meander and fork structures are used to assess yield across various pitch dimensions. Preliminary results demonstrate successful combo yield for pitches from 32nm to 20nm.
Authors
- Jan Doise (ORCID: https://orcid.org/0000-0002-9740-2668)
- Peter De Schepper (ORCID: https://orcid.org/0000-0001-7262-0709)
- Nobuyuki Fukui (ORCID: https://orcid.org/0000-0003-1044-1419)
- N. Guzman
- Víctor M. Blanco Carballo (ORCID: https://orcid.org/0000-0003-4308-0381)
- Cyrus Tabery
- Yannick Feurprier
- E. P. De Poortere
- Kathleen Nafus
- K. Vandersmissen (ORCID: https://orcid.org/0009-0008-7831-564X)
- Stéphane Larivière
- Chia-Yu Yao (ORCID: https://orcid.org/0000-0001-9771-041X)
- A. Hsu
- B. De Wachter
- Mahtab Sangghaleh
- Yusuke Wako
Institutions
- Tokyo Electron (Japan) (JP)
- Inpria (United States) (US)
- Intel (United Kingdom) (GB)
- ASML (Netherlands) (NL)
Publication Details
- Published
- 2025-06-02
- DOI
- https://doi.org/10.1109/iitc66087.2025.11075462
- Primary Topic
- Advancements in Photolithography Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00