Metal interconnection of high bandwidth memory in wafer level packaging

Growing demand for high-performance memory in AI applications has driven the adoption of high bandwidth memory, particularly in conjunction with micro-bump interconnects. While scaling down bump size enhances bandwidth and signal integrity, it introduces critical reliability challenges such as intermetallic compound overgrowth, Kirkendall void formation, solder wicking, and stress mismatch. Ni/SnAg micro-bump structures offer improved stability over Cu/Sn systems but present unique issues, especially under fluxless reflow and fine-pitch conditions. Solder wicking along Ni sidewalls and residual stress from grain coarsening in electroplated Ni layers degrade interconnect reliability. This study investigates these failure mechanisms and proposes mitigation strategies, including Sn alloying, surface oxide control, and grain refinement. Through microstructural and mechanical analysis, the research highlights the importance of material selection and process optimization to ensure the mechanical robustness and long-term reliability of advanced high bandwidth memory packaging under scaling requirements.