Thermal Performance Analysis of BSPDN and FSPDN From Chip to Package Level

Backside Power Delivery Network (BSPDN) has emerged as a promising solution to enhance power delivery efficiency in semiconductor devices. However, the thermal implications of this transition remain a critical challenge. This study employs finite element modeling to evaluate the heat dissipation characteristics of BSPDN in comparison to traditional power delivery architectures. The analysis considers multilayer heat transfer effects, including interconnect resistance, wafer thinning constraints, and bonding material properties. The results reveal that BSPDN exhibits a distinct heat dissipation profile, with thermal bottlenecks emerging within the BEOL region. Unlike conventional structures, where heat spreads efficiently through the silicon substrate, BSPDN necessitates alternative thermal pathways to mitigate self-heating effects. This work provides insight into the design trade-offs associated with BSPDN implementation and highlights the necessity for novel thermal management strategies in next-generation semiconductor systems.