A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth

This work presents an 8.5–14 GHz dual-path sampling phase detection (SPD)/phase frequency detection (PFD) phase-locked loop (PLL) (DP-SPFDPLL), with extended frequency/phase detection ranges, built-in frequency-locked loop (FLL) function, and stable loop bandwidth across PVT corners. An SPD and a PFD are placed on the dual paths, responsible for phase/frequency locking and temperature drift tracking. An SPD replica is introduced to align the locking points of the integral and proportional paths. A Slew Rate Calibration technique using a Ring Oscillator is proposed to make the slew rate of sampling ramps stable. Implemented in 7 nm FinFET, the 8.5–14 GHz DP-SPFDPLL achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$75~fs_{rms}$ </tex-math></inline-formula> integrated jitter and −252 dB PLL Figure-of-Merit (FoM)J.