A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning

Edge computing devices demand efficient transposable computing architectures to enable on-chip learning, necessitating novel hardware designs that balance performance and flexibility. We present an RRAM-based compute-in-memory macro capable of supporting both in-situ forward and backward propagation operations. The design incorporates an orthogonal-WL array structure with weight-level parallelism adjustment and a precision-driven input mechanism to enable flexible transposable computing. Additionally, optimized ADCs provide high throughput while maintaining area efficiency. The work exhibits a SOTA normalized area efficiency of 126.7 TOPS/mm2/bit, an energy efficiency of 2348.96 TOPS/W/bit, and a storage density of 4.84 Mb/mm2.

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Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3589580
Citations
2
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
1.46

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article

A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning

Jianshi Tang, Bin Gao, Lu Jie, Qiumeng Wei et al.
2 citations
IEEE Solid-State Circuits Letters
Advanced Memory and Neural Computing
1.46
article

A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning

Jianshi Tang, Bin Gao, Lu Jie, Qiumeng Wei, Huaqiang Wu, Sining Pan, Qingtian Zhang, Peng Yao, He Qian, Qi Qin, Dong Wu
article en
2 citations

Abstract

Edge computing devices demand efficient transposable computing architectures to enable on-chip learning, necessitating novel hardware designs that balance performance and flexibility. We present an RRAM-based compute-in-memory macro capable of supporting both in-situ forward and backward propagation operations. The design incorporates an orthogonal-WL array structure with weight-level parallelism adjustment and a precision-driven input mechanism to enable flexible transposable computing. Additionally, optimized ADCs provide high throughput while maintaining area efficiency. The work exhibits a SOTA normalized area efficiency of 126.7 TOPS/mm2/bit, an energy efficiency of 2348.96 TOPS/W/bit, and a storage density of 4.84 Mb/mm2.

IEEE Solid-State Circuits LettersVol. 8
Tsinghua University (CN)
National Natural Science Foundation of China, National Major Science and Technology Projects of China
Openalex Percentile: Top 16%
Advanced Memory and Neural Computing
1.46
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A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning — Jianshi Tang, Bin Gao, et al. · IEEE Solid-State Circuits Letters (2025) | TGRS Research Map | TGRS