Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process

This work presents a Time-to-Digital Converter (TDC) for Digital Phase-Locked Loops (DPLLs) applications featuring a dynamic power-reduction technique. The architecture, implemented in a 28-nm CMOS technology with a 0.9-V supply voltage and 250MHz sample rate, is able to reduce its power consumption up to 47% compared to the same TDC without the proposed solution, dissipating a minimum of 33μW during normal operation.