A Digital Imager Architecture with On-Chip Compression for High-Speed Imaging Applications

In response to the demand for high-resolution, high dynamic range, and high frame rate image sensors with low power consumption, the early 2000s saw a surge in research on on-chip compression techniques. These aimed to reduce data transmission bandwidth with minimal image quality degradation, balancing compression performance with CMOS planar technology limitations. Now, thanks to 3D integration and recent advancements in SPAD arrays and digital pixel sensors, these techniques are becoming interesting again. This work presents a novel sensor architecture suitable for digital imagers featuring on-chip compression. The proposed solution employing an in-pixel shot noise-based differential modulation scheme (DPCM) combined with an intra-pixel suppression scheme to exploits both temporal and spatial redundancies. Preliminary evaluations of compression performance through numerical simulations using synthesized videos of real scenes have demonstrated the advantages of the proposed solution achieving simultaneous high-fidelity image reconstruction (PSNR <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 28 ~\text{dB}$</tex>) and a high compression ratio at the same time (CR\~{}27). This reveals significant potential for further enhancements, paving the way for high speed and dynamic range imaging in various applications.