A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs

This paper presents a complementary (nMOS and pMOS) bootstrapped sampler. The proposed solution is implemented in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$28-\text{nm}$</tex> bulk CMOS technology with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.9-\mathrm{V}$</tex> supply voltage and integrated with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 5 0}$</tex>-MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Simulations demonstrate that this topology minimizes on-resistance modulation and charge injection effects, leading to a Total Harmonic Distortion (THD) enhancement of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-25-\mathbf{d B}$</tex> in the tens of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{M H z}$</tex> range and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-10-\text{dB}$</tex> above <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$900-\text{MHz}$</tex> compared to the conventional nMOS-based bootstrapped sampler.