A $256 \times 256$ SPAD Imager Architecture with Multi-Functional Pixel and High Temporal Aperture for Quantum Imaging Applications

In this paper we describe the architecture of a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 5 6} \times \mathbf{2 5 6}$</tex> Single Photon Avalanche Diode (SPAD) imager designed for quantum imaging applications in a 110 nm CMOS Sensor Imaging process. The chip features a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$256 \times 256$</tex> SPAD array with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$30 \mu \mathrm{m}$</tex> pitch and reconfigurable pixel multi-functionality i.e. photon counting with fast gating mode or continuous time stamping of time correlated events with an external trigger. The array is organized in macro-pixels composed of clusters of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> SPADs sharing the Time-to-Digital Converter (TDC), a logic arbiter circuit and other in-pixel circuitry reaching a remarkable <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\simeq 22 {\%}$</tex> Fill Factor despite the small pixel area. To optimize the usage of the available electronics, we designed an architecture which can share the in-pixel resources also among the neighboring macro-pixels laying on the same line. We split the chip in two independent halves with dedicated readout circuitry to improve the data throughput guaranteeing the possibility to sustain a maximum expected photon rate of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100 \text{Mphotons} / \mathrm{s}$</tex> impinging on the focal plane array. To this end, a row and a column zero-suppression logic circuit have been envisaged to save time during the matrix readout phase increasing the chip frame rate.

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Published
2025-06-23
DOI
https://doi.org/10.1109/icicdt65192.2025.11078087
Primary Topic
Advanced Optical Sensing Technologies
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article
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article

A $256 \times 256$ SPAD Imager Architecture with Multi-Functional Pixel and High Temporal Aperture for Quantum Imaging Applications

Leonardo Gasparini, Alessandro Tontini, Roberto Passerone, Enrico Manuzzato et al.
Advanced Optical Sensing Technologies
article

A $256 \times 256$ SPAD Imager Architecture with Multi-Functional Pixel and High Temporal Aperture for Quantum Imaging Applications

Leonardo Gasparini, Alessandro Tontini, Roberto Passerone, Enrico Manuzzato, Thomas Corradino, Luca Parmesan, Andrea Bonzi
article en

Abstract

In this paper we describe the architecture of a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 5 6} \times \mathbf{2 5 6}$</tex> Single Photon Avalanche Diode (SPAD) imager designed for quantum imaging applications in a 110 nm CMOS Sensor Imaging process. The chip features a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$256 \times 256$</tex> SPAD array with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$30 \mu \mathrm{m}$</tex> pitch and reconfigurable pixel multi-functionality i.e. photon counting with fast gating mode or continuous time stamping of time correlated events with an external trigger. The array is organized in macro-pixels composed of clusters of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times 2$</tex> SPADs sharing the Time-to-Digital Converter (TDC), a logic arbiter circuit and other in-pixel circuitry reaching a remarkable <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\simeq 22 {\%}$</tex> Fill Factor despite the small pixel area. To optimize the usage of the available electronics, we designed an architecture which can share the in-pixel resources also among the neighboring macro-pixels laying on the same line. We split the chip in two independent halves with dedicated readout circuitry to improve the data throughput guaranteeing the possibility to sustain a maximum expected photon rate of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100 \text{Mphotons} / \mathrm{s}$</tex> impinging on the focal plane array. To this end, a row and a column zero-suppression logic circuit have been envisaged to save time during the matrix readout phase increasing the chip frame rate.

University of Trento (IT), Fondazione Bruno Kessler (IT)
Openalex Percentile: Top 80%
Advanced Optical Sensing Technologies
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