Design of Low Power SRAM Memory Cell and Sense Amplifier Based on 20NM Technology

This paper presents and analyzes the design of a low power static random access memory (SRAM) and sense amplifier (SA) based on the 20nm technology node. With the rapid development of high performance computing and the increasing demand for energy efficient devices, reducing power consumption has become a key goal in integrated circuit design. The proposed SRAM cell employs advanced techniques that significantly reduce both static and dynamic power. The sense amplifier design further enhances power efficiency, reducing both static and dynamic power while maintaining high performance. Simulation results show a 21.7% reduction in dynamic power and a 15.42% reduction in static power for the proposed sense amplifier, with minimal delay increase. This research provides a promising solution for future low power memory designs, particularly suitable for high performance computing applications.