Phase-Locked Loop Design for 32Gbps/s High-Speed Serial Interface

In this paper, we propose a current-controlled ring oscillator Phase-Locked Loop (PLL) architecture with adaptive frequency control to address process variation tolerance and nonlinear jitter challenges in high-speed serial interface clock circuits. Through optimized Charge Pump (CP) structure and dynamic loop bandwidth adjustment, the implemented SMIC 28nm design achieves 1.5-8GHz continuous tuning range while suppressing reference spur-induced jitter. Measurement results demonstrate an 8GHz quadrature clock output with -115.7dBc/Hz phase noise at 1MHz offset under 1V supply voltage and 500MHz reference input, achieving 900ns lock time. Occupying 0.085mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area and consuming 7.48mW, the proposed PLL enhances process variation tolerance compared to conventional designs while meeting stringent jitter requirements for SerDes applications.