Design of Reconfigurable Baseband Receiving Circuit with Variable Gain and Bandwidth

This paper presents an analog baseband receiving circuit designed in 28nm CMOS technology. The circuit primarily comprises a variable gain amplifier (VGA) and a tunable bandwidth filter (TBF). The VGA employs the cascade structure consisting of the digital-controlled attenuator and a low-noise amplifier. The TBF implements a two-stage 4th-order Chebyshev low-pass filter utilizing an improved multiple-feedback (MFB) architecture to optimize stopband attenuation. The whole circuit achieves a 32 dB adjustable gain range with 0.5 dB steps while providing a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$15 \text{MHz} / 25 \text{MHz} / 50 \text{MHz} / 100 \text{MHz} / 200 \text{MHz}$</tex> switchable bandwidth for all gain modes. Simulation results demonstrate that the receiver circuit exhibits the noise figure below 20 dB at 10 MHz and an output 1 dB compression point exceeding <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 0} \mathbf{d B m}$</tex>.