A High-Resolution Two-Stage Coarse-to-Fine Pipelined-SAR ADC

This paper presents a high-resolution, two-stage coarse-to-fine pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with asynchronous timing. The design employs a two-stage structure with 6-bit and 8-bit configurations. Both stages utilize a binary-split Capacitor Digital-to-Analog Converter (CDAC) with bottom-plate sampling, and the SAR logic is implemented using a Vcm-based switching scheme. Additionally, the design incorporates a charge-pump bootstrapped switch, a two-stage dynamic comparator, and a gain-boosting residue amplifier. The circuit was fabricated and simulated in a 65-nm CMOS process. Simulation results demonstrate that under a 1.2-V supply voltage and 100-MS/s sampling rate with a full-scale sinusoidal input, the ADC achieves an ENOB of 11.61 bits, an SNDR of 71.63 dB, an SFDR of 85.81 dB, and the ADC consumes 16.35 mW, indicating robust performance across all metrics.