A 50MHz Digitally Controlled Integrated Voltage Regulator with 92.8% Peak Efficiency

This paper presents a digitally-controlled four-phase high-frequency buck converter operating at 50-MHz switching frequency. The proposed voltage regulator achieves a peak efficiency of 92.88% during 1.8V-to-1V conversion under 4A load conditions. The digital control system incorporates several innovative techniques: a windowed flash ADC operating at 200MHz oversampling frequency for power optimization, digital trimming enabling comparator calibration within 1/2 LSB for enhanced precision, and a hybrid DPWM architecture combining counter and delay-line techniques with dual-edge modulation. The delay line implementation achieves 20ps resolution by leveraging the minimum delay of the process. Experimental results show satisfactory transient response, with undershoot limited to 105mV during load transitions between 4A and 16A, while maintaining significant improvements in circuit simplicity and control latency reduction.

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Publication Details

Published
2025-07-11
DOI
https://doi.org/10.1109/eicct65471.2025.11099814
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

A 50MHz Digitally Controlled Integrated Voltage Regulator with 92.8% Peak Efficiency

Zhenxing He, Wanyuan Qu, Lei Liu, Tao Zhang
Analog and Mixed-Signal Circuit Design
article

A 50MHz Digitally Controlled Integrated Voltage Regulator with 92.8% Peak Efficiency

Zhenxing He, Wanyuan Qu, Lei Liu, Tao Zhang
article en

Abstract

This paper presents a digitally-controlled four-phase high-frequency buck converter operating at 50-MHz switching frequency. The proposed voltage regulator achieves a peak efficiency of 92.88% during 1.8V-to-1V conversion under 4A load conditions. The digital control system incorporates several innovative techniques: a windowed flash ADC operating at 200MHz oversampling frequency for power optimization, digital trimming enabling comparator calibration within 1/2 LSB for enhanced precision, and a hybrid DPWM architecture combining counter and delay-line techniques with dual-edge modulation. The delay line implementation achieves 20ps resolution by leveraging the minimum delay of the process. Experimental results show satisfactory transient response, with undershoot limited to 105mV during load transitions between 4A and 16A, while maintaining significant improvements in circuit simplicity and control latency reduction.

Zhejiang University (CN)
Affordable and clean energy
Openalex Percentile: Top 81%
Analog and Mixed-Signal Circuit Design
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A 50MHz Digitally Controlled Integrated Voltage Regulator with 92.8% Peak Efficiency — Zhenxing He, Wanyuan Qu, et al. · (2025) | TGRS Research Map | TGRS