Design of an SRAM-Based Computing-in-Memory Multiply-Accumulate Circuit for Image Processing

With the rapid advancement of artificial intelligence, deep learning models have been widely applied in image processing. However, high energy consumption limits their deployment on resource-constrained edge devices. This paper proposes an SRAM-based Multiply-Accumulate (MAC) circuit tailored for compute-in-memory (CIM) image processing systems to enhance energy efficiency. The design incorporates dual positive/negative weight arrays to handle signed operations, a MAC unit leveraging MOSFET current sources and switches for efficient analog multiplication, and a high-speed, high-precision column-parallel current-to-voltage conversion circuit to boost computational performance. Simulation results demonstrate that, in an image exposure enhancement task, the output image achieves a mean squared error (MSE) of 45.87, a structural similarity index (SSIM) of 0.97, and a peak signal-to-noise ratio (PSNR) of 31.52 dB. Operating at 1.8 V, the circuit delivers a throughput of 13.6 GOPS, with a power consumption of 9.1 mW and an energy efficiency of 1.49 TOPS/W, which achieves a 21.1% improvement over digital architectures.