8T SRAM CIM Based on Interleaved Adder Tree Structure

This paper aims to design an SRAM (Static Random-Access Memory) circuit with in-memory computing capabilities and proposes a multiplication operation structure, including an in-memory computing unit and an Adder Tree circuit. This structure needs to cooperate with other modules of the circuit to achieve in-memory computation. The in-memory computing unit consists of a transmission unit and a 6T SRAM cell, where the 6T SRAM cell is used for weight storage, and the transmission unit performs multiplication operations between the weights and input signals while transmitting the computation results to the output precharge circuit. The Adder Tree circuit adopts a novel 6T-2ST hybrid design. This approach effectively reduces the number of transistors required for in-memory computation, minimizing area and power consumption, thereby improving energy efficiency.