A PyMTL-Based Connectivity Verification Platform for Interface Model

The continuous scaling of semiconductor process nodes has driven the miniaturization of transistor feature sizes, significantly enhancing chip integration density while simultaneously causing exponential growth in design complexity. Very large-scale integrated circuits now encompass pin counts reaching thousands of nodes, posing unprecedented challenges to connectivity verification of interface models. To address these challenges, the hardware design domain is increasingly adopting high-level general-purpose programming languages to extend or replace traditional VHDL/Verilog methodologies. This paper develops a hierarchical and highly reusable connectivity verification platform based on the PyMTL framework, employing a systematic verification methodology to validate interface model connectivity. We conducted connectivity verification tests on the SPI interface and SRAM interface using a connectivity verification platform, and the experimental results demonstrated the functionality of the connectivity verification platform.