Low-Power Phase-Locked Loop Design: Co-Optimization of Subthreshold VCO and Adaptive Capacitive Tuning

The phase-locked loop (PLL) is a core component of high-precision clock circuits and plays a vital role in system-on-chip (SoC) systems. Compared to digital PLLs, analog charge pump PLLs (CPPLLs) offer higher frequency resolution and are widely used in sensor imaging and vehicle-assisted driving systems. This report first compares the advantages and disadvantages of Class I and Class II PLLs, then compares the first-order, second-order, and third-order loop filters, and finally designs a third-order Class II charge pump PLL using the 130nm CMOS process. During the design, we focused on the study of electrical mismatch in the frequency and phase detector and the charge pump module, and proposed effective solutions for clock feed-through, charge injection, and charge sharing. For the ring oscillator, we adopted a fully differential structure to enhance the power supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) of the circuit, and proposed effective solutions for the degeneracy state of even-order ring oscillators. For the loop filter, we prioritized the stability of the entire system, ensuring system stability while combining parameters obtained from simulations of other modules to determine the coefficients of the loop filter. The PLL designed in this report has an output clock frequency range of 790MHz-2.48GHz, with the final output frequency set at 1GHz. The lock-in frequency error is less than 1%, the eye diagram jitter peak-to-peak is 13ps, and the Vc jitter is 11mV.