A Hardware Accelerator Based on Unstructured Pruning for One-Dimensional Sparse Convolutional Neural Networks in Arrhythmia Detection

This work presents a hardware accelerator for one-dimensional sparse convolutional neural networks (1D-SCNN) based on unstructured pruning, designed to enhance computational efficiency in arrhythmia detection while minimizing power consumption and resource usage. The proposed architecture leverages a block-flattened sparse weight storage format and an optimized index matching circuit to efficiently handle sparse computations. The accelerator was prototyped on an FPGA Zynq XC7Z045, achieving an inference throughput of 24.6 GOP/s with power consumption of 0.54 W, resulting in an energy efficiency of 45.56 GOP/s/W. Experimental results demonstrate that the pruned 1D-VGG16 model maintains an accuracy of 99.13% for arrhythmia classification at 70% sparsity, confirming the effectiveness of the proposed approach. This work provides a promising solution for deploying deep learning models in low-power, resource-constrained edge devices, particularly in biomedical applications such as wearable ECG monitoring.