A prototype pixel readout chip with column-level ADCs for high frame rate XFEL applications

Abstract X-ray Free Electron Laser (XFEL) facilities can deliver femtosecond X-ray pulses with ultra-high peak brightness, which in turn calls for high performance integrating-type pixel detectors. This work proposes a pixel readout ASIC (Application Specific Integrated Circuit) chip featuring a digital readout architecture designed to operate at a frame rate of 10 kHz for applications at next generation XFELs. The proposed design achieves a broad detection range from single-photon sensitivity to 10^4 photons at 12 keV by incorporating the dynamic gain-switching technique in the pixel front-end circuit. Each pixel column integrates an 11-bit SAR ADC, ensuring fast and accurate conversion of analog signals into digital domain. The digitized data is then transmitted via a serial chip interface. A small-scale prototype chip, consisting of a 16 × 16 pixel array, was designed and fabricated using a 130 nm CMOS process to validate the proposed architecture. This paper presents the design and experimental results of the prototype chip.