Analog Comparator Modeling and Selection for High-Speed Constant On-Time Controlled DC-DC Converters

The Constant-On-Time (COT) control architecture is widely used in modern voltage regulator modules (VRMs), especially in computational processing applications, due to its high efficiency under light-load conditions and its fast transient response. Popular variants such as current-mode (CM-COT) and ripple-based (RB-COT) approaches offer improved transient responses to load or reference steps. However, these methods depend on ripple sensing and comparison logic for power modulation, and these signals are susceptible to interference, which can potentially cause subharmonic oscillations. While solutions like RC filtering and slope compensation are feasible, they require additional components and design considerations. This study proposes an analog approach to modeling and analyzing comparator delay, which inherently enhances the system's resilience against interference, thereby improving control loop stability. Both simulations and experimental results validate the effectiveness of the proposed comparator delay model in addressing stability issues in CM-COT and RB-COT controlled power converters.