Degradation Characterization of Safe Operating Area of IGBT Devices Considering Aging Affects

With the expanding use of insulated gate bipolar transistors (IGBTs) in modern power electronics systems, ensuring their operational reliability throughout extended service life has become a critical research focus. While conventional safe operating area (SOA) specifications effectively define the electrical stress tolerance limits for pristine devices, they inadequately address the progressive package degradation induced by coupled electrical-thermal-mechanical stresses during prolonged field operation. In this paper, a degradation characterization model of IGBT safe operating area considering the influence of package aging is established. Combined with the selection of device aging characteristic parameters, mathematical model construction and experimental verification, the dynamic SOA definition of IGBT device considering the influence of aging is realized. The definition of cumulative damage is analyzed to quantify the fatigue degree of the solder layer, and the junction-shell thermal resistance degradation and SOA boundary shrinkage process are described. The power cycle experimental results verify the correctness of the model. Further combining the power cycle and practical application scenarios, the effects of different junction temperature fluctuation operating conditions on the SOA degradation of the device are proposed. The results show that the larger the junction temperature fluctuation is, the more obvious the thermal resistance degradation of the device is, and the larger the SOA shrinkage of the device is, indicating that different junction temperature fluctuations caused by changes in operating conditions such as load and ambient temperature are important factors affecting the SOA boundary shrinkage of the device. Through the TCAD simulation of the chip cell level, it is analyzed that the increase of the junction temperature in the later stage of the device aging leads to the decrease of the avalanche tolerance of the chip, which is more likely to cause the avalanche breakdown failure of the device and cause the further degradation of the safe working area of the device.