A 600 MHz, 3.57 $\text{ps}_{R M S}$ Jitter, 1.84 mW Power Consumption Phase Locked Loop in 12nm FinFET

This paper presents a single loop type-II Phase Locked Loop (PLL) designed in 12nm FinFET technology. This PLL's main purpose is to work as an on-chip clock generator for digital circuits, generating a low-jitter output clock at 600 MHz output frequency with a reference clock of 100 MHz. The system features a Voltage Controlled Oscillator (VCO) implemented as a 4-stage fully differential ring oscillator with symmetric loads, with a dedicated half-replica bias circuit and an OPAMP-style differential to single-ended converter. The proposed design of the analog components allows for a fast lock time and a good trade-off between output jitter and total power consumption. The correct operation of the PLL was assessed through simulations under nominal conditions and under PVT variations at the schematic level. Performance was evaluated with post-layout simulations, showing 3.57 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{ps}_{R M S}$</tex> of integrated jitter with 1.84 mW total power consumption at 0.8 V supply voltage, scoring a jitter Figure of Merit (FoM) of -226.3 dB. The total area occupied is 0.011 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.