Design for Reliability of Multi-Bit Operations in RRAM-Based SIMPLY Logic-in-Memory Circuits

The Smart Material Implication Logic (SIMPLY) enables the computation of logic operations directly within the memory array, leading to considerable energy efficiency by bypassing the von Neumann bottleneck. Moreover, it has been already proven that the use of Resistive Random Access Memory (RRAM) devices within the SIMPLY architecture allows multi-bit operation. Here we design the full SIMPLY cell for the reliable execution of the multi-bit read operation (i.e., the most critical one), considering both RRAM variability and process variations in the peripheral circuitry of the array designed in a 130 nm CMOS technology. The results demonstrate that CMOS process variations significantly impact on the bit error rate (BER). Nevertheless, with appropriate circuit design, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\operatorname{BER}&lt;10^{-6}$</tex> can be achieved for 2- and 3-bit SIMPLY operations.