A Low-Power Supply-Independent Analog Clock Frequency Divider for About 100 Division Factor

This paper presents an Analog Clock Frequency Divider (CFD) implemented in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.35 \mu \mathrm{m}$</tex> technology, designed for ultra low-power operation in automotive applications during idlemode. The proposed CFD is designed with a double capacitive system and a comparator to achieve a division factor of about 100. The methodology has been validated through simulations and experimental measurements. The fabricated device achieves a measured division factor of 88. The device operates with an average power consumption of 96 nW at a 3V supply, with 62 nW consumed by the comparator and 34 nW by the capacitive system. The total area occupied by the frequency divider is 7000 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{m}^{2}$</tex>, with 4800 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{m}^{2}$</tex> dedicated to capacitors. Experimental results show a total variation of 2% over a temperature range from - 40°C to 100°C.