A 14-bit SAR ADC with a low-power comparator

Based on the TSMC 0.18μm CMOS process, this paper presents the design of a 14-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) integrated with a low-power dynamic comparator. The overall architecture adopts a fully differential structure, effectively suppressing common-mode noise and improving system linearity. Additionally, a three-segment capacitor array structure is employed to ensure DAC linearity while reducing the number of capacitors used, thereby minimizing circuit area and power consumption. To address the high-power consumption issue of traditional two-stage dynamic comparators, this paper proposes an improved low-power two-stage dynamic comparator. By adding a tail capacitor in the pre-amplification stage, unnecessary charge loss is reduced, leading to approximately a 17% reduction in power consumption, thereby enhancing overall energy efficiency. The design is validated through simulations using Cadence software. Under a supply voltage of 1.8V and a sampling rate of 500KS/s, the SAR ADC achieves an effective number of bits (ENOB) of 13.31, a signal-to-noise and distortion ratio (SNDR) of 79.26 dB, and a spurious-free dynamic range (SFDR) of 88.45dBc, demonstrating excellent dynamic performance and low power consumption. The simulation results indicate that the proposed SAR ADC exhibits outstanding performance in low-power and high-precision applications, making it well-suited for biomedical signal processing and similar fields.