Improving Irradiation Reliability of 4H-SiC 1200V LDMOS and 20V CMOS Logic Circuits with Leakage Current Blocking Technology

Replacing silicon large-scale integrated circuits (ICs) with silicon carbide (SiC) large-scale ICs can significantly enhance the radiation hardness of power electronic systems. High voltage lateral diffused metal oxide semiconductor (LDMOS) and low-voltage CMOS logic circuits are the two key elements that make up large-scale power ICs. It is found in this work that the positive charge traps generated after Total Ionizing Dose (TID) irradiation induce unexpected leakage paths, resulting in premature breakdown of LDMOS and degraded output voltage swing of logic circuits, while for Single-Event (SE) irradiation, increased leakage current leads to the latch up, and then device/circuit failure. An economical reinforcement technology with floating <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}+/ \mathrm{P}+$</tex> rings and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}+$</tex> strips is proposed. Breakdown voltage (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$B V$</tex>) of the SiC LDMOS with the reinforcement technology can be increased from 692 V to 1250 V at TID <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$=300 \text{kGy}$</tex>. For reinforced logic circuit with full voltage swing, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 3$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 1.44$</tex> improvements in TID and SE irradiation endurances can be obtained, respectively, enabling robust operation in aerospace and nuclear applications.