A 32-Channel 196-$\boldsymbol{\mu} \mathbf{W}$ Logarithmic SoC for Brain Network Connectivity Extraction and Adaptive Psychiatric Symptom Classification

This paper presents a 32-channel brain-computer interface SoC for closed-loop deep-brain stimulation in psychiatric disorders. The SoC integrates a 32-channel analog front-end, an efficient logarithmic feature extraction engine, a neural additive model classifier with online update, and a multimode stimulation controller. Fabricated in 65 nm CMOS, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.46 ~\text{mm}^{2}$</tex> SoC consumes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6.14 \mu ~\mathrm{W} /$</tex> channel, enabling accurate, low-power, and adaptive detection of psychiatric states.