Critical Role of Quantum Confinement on Transfer Length in Achieving High-Performance In<sub>2</sub>O<sub>3</sub> Transistors with Ultra-Scaled Contacted Gate Pitch
In this work, for the first time, we study the contact length <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(\mathrm{L}_{\mathrm{C}}\right)$</tex> and contacted gate pitch (CGP) scaling in ultrathin <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{In}_{2} \mathrm{O}_{3}$</tex> field-effect transistors (FETs). A large 53 % decrease in transfer length (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{T}}$</tex>) from 76 to 36 nm can be observed by increasing the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{In}_{2} \mathrm{O}_{3}$</tex> channel thickness (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{ch}}$</tex>) from 1.2 nm to 2.0 nm, which can be understood by the positive-to-negative Schottky barrier height (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Phi_{\text{SB}}$</tex>) transition modulated by the quantum confinement (QC) effect in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{In}_{2} \mathrm{O}_{3}$</tex> channel. Leveraging the record-low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\mathrm{T}}$</tex> of 36 nm optimized by the QC, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.0 \text{nm} \text{In}_{2} \mathrm{O}_{3}$</tex> FETs demonstrate a record-low contact resistance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}_{\mathrm{C}}$</tex>) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$140 \Omega \cdot \mu$</tex> m and a record-high maximum drain current (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\mathrm{D}, \max}$</tex>) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.57 \text{mA} / \mu \mathrm{m}$</tex> at ultrascaled CGP of 80 nm among all reported oxide semiconductor FETs with CGP scaling.
Authors
- Chang Niu (ORCID: https://orcid.org/0000-0003-3175-7164)
- C.H. Liu (ORCID: https://orcid.org/0009-0006-8509-3569)
- Jian-Yu Lin (ORCID: https://orcid.org/0000-0002-8800-8714)
- Peide D. Ye (ORCID: https://orcid.org/0000-0001-8466-9745)
- Zehao Lin (ORCID: https://orcid.org/0000-0002-5308-1065)
- Juanjuan Lu (ORCID: https://orcid.org/0000-0003-4885-8287)
- Haiyan Wang (ORCID: https://orcid.org/0000-0003-2859-0519)
Institutions
- Purdue University West Lafayette (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074856
- Citations
- 2
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 1.46