Novel Ultra-Thin Transistor Layer Transfer (TLT) Technology for Demonstrating Wafer-Level nm-Scale 3-Layer Stacking to Enable Multi-Tier Transistors and Backside PDN of a 3D Vertical FET Architecture

A new wafer-level transistor layer transfer (TLT) technology based on Smart Cut <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${}^{\text{TM}}$</tex> and IR laser release processing is reported to target on nm-scale ultra-thin multi-tier stacking. This innovation demonstrated 3-layer stacking with minimum Si thickness less than 300 nm and layer-to-layer isolation dielectric thinner than 40 nm under low thermal budget (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;350^{\circ} \mathrm{C}$</tex>) for the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1^{\text{st}}$</tex> time. This TLT stack shows good wafer warpage (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;60 \mu \mathrm{m}$</tex>) and small total thickness variation (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;2 \text{nm}$</tex>) across wafer. Moreover, it was further hybrid bonded with a Si wafer (4-layer wafer stack in total) to reveal the possibility of functional SoC integration. An integration flow with the TLT technology as backbone is proposed to enable a 3D vertical FET structure composited multi-tier transistor-stacking, backside PDN integration, and cascaded contact plug formation.