SRAM Scaling Opportunities Below .01 \mu ~\mathrm{m}^{2}$ Using Double-Row CFET Architecture with Wordline-Folded Bitcell Design for Performance Optimization

This work presents a DTCO exploration that enables SRAM scaling below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.01 \mu ~\mathrm{m}^{2}$</tex> in CFET nodes, achieving over 50% scaling compared to the A14 nanosheet node. It focuses on simplifying SRAM bitcell internal routing in CFET architecture, identifying process integration modules required for a compact CFET bitcell, and proposing design approaches to optimize performance. The DTCO study demonstrates that designing two bitcells together in a wordline-folded configuration, compared to bitcells without WL-folding, improves performance by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times$</tex>, enhances write margin by 162 mV, and enables a standard cell-like layout.