Realistic and Scalable TCAD for Yield-Aware Full-Chip DTCO

Recent advances in AI-based virtual metrology and physics-based modeling have accelerated the realization of digital twins, enabling comprehensive analysis. In this paper, we propose a methodology to evaluate chip-level defect probabilities and thermal bottlenecks, followed by a physical layout optimization strategy. Our framework integrates multi-environment virtual metrology with a neural-network-based 3D real-time TCAD model, enabling the analysis of billions of geometries and thermal hotspots for simultaneous yield and performance optimization. Validated on a modest HPC cluster, our full-chip simulation completes in under an hour. This study extends the role of TCAD from device-level analysis to chip-level design, linking performance and yield interactions and establishing a new milestone in the DTCO paradigm.

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Publication Details

Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075051
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.67

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article

Realistic and Scalable TCAD for Yield-Aware Full-Chip DTCO

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1 citations
Analog and Mixed-Signal Circuit Design
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article

Realistic and Scalable TCAD for Yield-Aware Full-Chip DTCO

S.M. Kim, Dae Sin Kim, Min‐Chul Park, Segab Kwon, Jae-Hyun Kang, Hong-Hyun Park, Joong-Won Jeon, Sangyeon Kim, Young-Gu Kim, Jihye Lee, Jae-Hwan Kim, Sojung Lee, Yeji Kim, Changwook Jeong, Yoon‐Suk Kim, Byung-Chul Shin, Hyunjae Jang, Nam‐Jae Kim, Usuk Chae
article en
1 citations

Abstract

Recent advances in AI-based virtual metrology and physics-based modeling have accelerated the realization of digital twins, enabling comprehensive analysis. In this paper, we propose a methodology to evaluate chip-level defect probabilities and thermal bottlenecks, followed by a physical layout optimization strategy. Our framework integrates multi-environment virtual metrology with a neural-network-based 3D real-time TCAD model, enabling the analysis of billions of geometries and thermal hotspots for simultaneous yield and performance optimization. Validated on a modest HPC cluster, our full-chip simulation completes in under an hour. This study extends the role of TCAD from device-level analysis to chip-level design, linking performance and yield interactions and establishing a new milestone in the DTCO paradigm.

ON Semiconductor (United States) (US), Samsung (South Korea) (KR), Samsung Pharm (South Korea) (KR), Ulsan National Institute of Science and Technology (KR)
National Research Foundation, Korea Institute for Advancement of Technology, Ministry of Science and ICT, South Korea, Samsung
Openalex Percentile: Top 28%
Analog and Mixed-Signal Circuit Design
0.67
DOISourceOpenAlex
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