Effects of Adjacent Floating Metal Interconnect Through Plasma-Induced Coupling

3D NAND memories have been developed by increasing cell stack height, which accompanies strong plasma energy to achieve high aspect ratio. Plasma-induced current causes high bias voltage stress during the fabrication, finally leading to gate oxide breakdown or wafer arcing [1]. Although plasma damage has been studied for a long time, the effects of the floating metal interconnects during the plasma charging processes have been less concerned. This study aims for completeness of layout design guidelines for metal interconnects by presenting various cases of electromigration (EM) failure and suggesting a new index of plasma-induced damage (PID), which can prevent unexpected changes or failures in electrical properties under plasma charging environments.