An 88.8dB-SNDR 6-MS/s Pipelined SAR ADC with A Closed-Loop Dynamic Amplifier Featuring Highly-Linear Full-Scale Output Swing

This paper presents a pipelined SAR ADC with a two-stage closed-loop residue amplifier (RA). The proposed RA incorporates a floating gm-ratio-based amplifier (FGA) as the first stage and a charge-pump-assisted cascoded floating inverter amplifier (CP-FIA) as the output stage. It enables fast-slewing, energy-efficient, robust, and highly-linear amplification, with a THD of <-100 dB at full-scale output swing. A system-level chopping-assisted auto-zero (AZ) is adopted to eliminate the RA's flicker noise and offset without additional thermal noise penalty. The prototype achieves 88.8dB SNDR at 6MS/s, demonstrating the best FoMs of 183dB among ADCs with >5MS/s conversion rate.