Performance Step-Up in PMOS with Monolayer WSe<sub>2</sub> Channel

This study makes monolayer (1L) tungsten diselenide (WSe2) more competitive as a scaled p-channel candidate. We address performance constraints related to channel, dielectric, and contact while reducing device-to-device variability. Back-gated PMOS with 1L-WSe2 channel and effective oxide thickness (EOT) of 1.2 nm reaches ON-current of 400 µA/µm at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> of -1 V, with subthreshold swing of 72 mV /decade, ON/OFF ratio of 7 orders, nearly hysteresis-free, while operating in enhancement-mode. Furthermore, passivation allowing for air stability is implemented without performance degradation. This is achieved without the use of materials that are not compatible with wet processing. We identify contact resistance and specifically the need for gate-voltage-independent contact resistance as the main next step for improving device performance.

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Publication Details

Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11075167
Citations
2
Primary Topic
2D Materials and Applications
Type
article
Field-Weighted Citation Impact
1.04
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article

Performance Step-Up in PMOS with Monolayer WSe2 Channel

Wei‐Sheng Yun, Terry Y.T. Hung, Chih‐I Wu, Wen‐Hao Chang et al.
2 citations
2D Materials and Applications
1.04
article

Performance Step-Up in PMOS with Monolayer WSe2 Channel

Wei‐Sheng Yun, Terry Y.T. Hung, Chih‐I Wu, Wen‐Hao Chang, Wen-Chia Wu, G. Vellianitis, Min Cao, Iuliana Radu, Sui-An Chou, Dawei Heh, Mengzhan Li, Seul Ku, Goutham Arutchelvan, Ang‐Sheng Chou, Po‐Sen Mao, Yu-Tung Lin, Po‐Hsun Ho, Mark van Dal, Chao-Ching Cheng, Mingyang Li, Yu-Wei Hsu, Chen‐Feng Hsu, Ching-Hao Hsu, Y. C. Chiu
article en
2 citations

Abstract

This study makes monolayer (1L) tungsten diselenide (WSe2) more competitive as a scaled p-channel candidate. We address performance constraints related to channel, dielectric, and contact while reducing device-to-device variability. Back-gated PMOS with 1L-WSe2 channel and effective oxide thickness (EOT) of 1.2 nm reaches ON-current of 400 µA/µm at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> of -1 V, with subthreshold swing of 72 mV /decade, ON/OFF ratio of 7 orders, nearly hysteresis-free, while operating in enhancement-mode. Furthermore, passivation allowing for air stability is implemented without performance degradation. This is achieved without the use of materials that are not compatible with wet processing. We identify contact resistance and specifically the need for gate-voltage-independent contact resistance as the main next step for improving device performance.

National Yang Ming Chiao Tung University (TW), National Taiwan University (TW), Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Openalex Percentile: Top 23%
2D Materials and Applications
1.04
DOISourceOpenAlex
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