A 0.8\mu\mathrm{m}$ 32Mpixel Always-On CMOS Image Sensor with Windmill-Pattern Edge Extraction and On-Chip DNN

This paper presents a CMOS image sensor (CIS) that integrates two operation modes: a high-resolution viewing mode with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.8 \mu \mathrm{m}$</tex> 32Mpixels and a low-power always-on object recognition mode consuming 2.67 mW at 10 fps. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An on-chip DNN processor was implemented alongside a compact algorithm with only 12 KB for coefficients and 48 KB for working memory. The design incorporates separate circuit areas for high-speed viewing and low-power sensing modes, thereby ensuring optimal performance and energy efficiency.

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Publication Details

Published
2025-06-08
DOI
https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074825
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
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article

A 0.8\mu\mathrm{m}$ 32Mpixel Always-On CMOS Image Sensor with Windmill-Pattern Edge Extraction and On-Chip DNN

Kazutaka Yasuda, Ota K, C. Takano, Kazutoshi Haraguchi et al.
CCD and CMOS Imaging Sensors
article

A 0.8\mu\mathrm{m}$ 32Mpixel Always-On CMOS Image Sensor with Windmill-Pattern Edge Extraction and On-Chip DNN

Kazutaka Yasuda, Ota K, C. Takano, Kazutoshi Haraguchi, Keiji Matsuda, Setsuo Minami, M. Tsuruta, K. Yamanaka, Motoyuki Sato, Yosuke Ueno, Etsushi Kato, Garuda FUJII, Makoto Watanabe, Akihiko Kato, K. Yasuoka, Katsurou Hanzawa, Sachio Akebono
article en

Abstract

This paper presents a CMOS image sensor (CIS) that integrates two operation modes: a high-resolution viewing mode with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.8 \mu \mathrm{m}$</tex> 32Mpixels and a low-power always-on object recognition mode consuming 2.67 mW at 10 fps. The CIS features a unique windmill-pattern analog edge extraction circuit that is resilient to illumination variations. An on-chip DNN processor was implemented alongside a compact algorithm with only 12 KB for coefficients and 48 KB for working memory. The design incorporates separate circuit areas for high-speed viewing and low-power sensing modes, thereby ensuring optimal performance and energy efficiency.

Affordable and clean energy
Openalex Percentile: Top 82%
CCD and CMOS Imaging Sensors
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A 0.8\mu\mathrm{m}$ 32Mpixel Always-On CMOS Image Sensor with Windmill-Pattern Edge Extraction and On-Chip DNN — Kazutaka Yasuda, Ota K, et al. · (2025) | TGRS Research Map | TGRS