First Demonstration of 9N+9P Complete Dipole Multi-V_Ts CMOS Integration with Atomic Interfacial Dipole Buffer Layer Technique in GAA NSFETs

For the first time, we reported one complete dipole CMOS integration with atomic interfacial dipole buffer layer (AIDBL) technique for WFM-free multi- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{T}}$</tex> modulation technology. With novel dual dipole-first integration process, various dipole tuning and AIDBL linear <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{T}}$</tex> modulation capabilities, the experimental CMOS integration on GAA NSFETs were successfully established and the devices achieved symmetric 9N+9P level multi- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\mathrm{T}}\mathrm{s}$</tex> within ~800 mV, which providing one promising method to effectively reduce challenging <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{sus}}$</tex> space for WFM filling and then enhance the transistor driving performance for future transistor technology.