A 31.5-36 GHz Low-Spur Gain-Boosting Charge-Sharing Locking PLL with 54fs Jitter

We propose a gain-boosting (GB) charge-sharing locking (CSL) PLL that achieves both ultra-low jitter and low reference spur. The GB-CSL mechanism reads the charge residue of CSL via an ADC, amplifies it digitally, and precharges it back via a DAC with a small charge-sharing capacitor Cshare coupled to the LC-tank. This significantly enhances the PLL bandwidth <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\text{BW}}$</tex>, resulting in low rms jitter while minimizing load modulation to the LC-tank. Implemented in 28-nm CMOS, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 33-\text{GHz}$</tex> PLL achieves 54 fs rms jitter and a low reference spur of -66 dBc, while consuming 14 mW.