An NS-SAR Quantizer-Based Pipeline Incremental Delta-Sigma ADC Using a Current-Regulated Floating Ring Amplifier and Two-Phase Miller Negative-C

A pipeline incremental ADC (IADC) leverages a 6-bit noise-shaping SAR quantizer for high SQNR at low OSR. A pipeline IADC structure enables continuous sampling and concurrent stage processing, improving bandwidth. Delay-free integrators and residue amplification enhance signal accumulation, boosting SQNR. A current-regulated floating ring amplifier (CURE FLORA) halves power consumption, while a two-phase Miller Negative-C technique mitigates integrator gain errors. Implemented in 28-nm CMOS, the prototype achieves an SNDR of 80.1 dB, SFDR of 97.2 dB, at 80 MS/s over a 5 MHz bandwidth. With a power consumption of 1.85 mW, the Walden FoM and Schreier SNDR FoM of 22.4 fJ/conversion-step and 174.4 dB, respectively.