Performance Comparison of 6T SRAM and Hybrid SRAM-DRAM Architectures for IoT Applications

With the increasing demand for energy-efficient memory solutions in Internet of Things (IoT) and edge computing applications, designing optimized memory architectures has become crucial. This paper presents a comparative study of a conventional 6T SRAM cell and a hybrid SRAM-DRAM architecture, both evaluated for their power efficiency and performance. The 6T SRAM cell, previously validated for low power consumption and enhanced stability, is implemented alongside a custom hybrid SRAM-DRAM structure.Using the Cadence Virtuoso platform with the GPDK 45nm process technology, the hybrid SRAM-DRAM architecture demonstrates a significant reduction in power consumption, from 170.15 µW in 6T SRAM to 127.77 µW, highlighting its suitability for low-power applications. These findings establish the hybrid architecture as a promising candidate for next-generation memory systems.

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Publication Details

Published
2025-05-23
DOI
https://doi.org/10.1109/iccc64910.2025.11077211
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

Performance Comparison of 6T SRAM and Hybrid SRAM-DRAM Architectures for IoT Applications

H S Gopika, O P Amritha, E Resmi
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Low-power high-performance VLSI design
article

Performance Comparison of 6T SRAM and Hybrid SRAM-DRAM Architectures for IoT Applications

H S Gopika, O P Amritha, E Resmi
article en

Abstract

With the increasing demand for energy-efficient memory solutions in Internet of Things (IoT) and edge computing applications, designing optimized memory architectures has become crucial. This paper presents a comparative study of a conventional 6T SRAM cell and a hybrid SRAM-DRAM architecture, both evaluated for their power efficiency and performance. The 6T SRAM cell, previously validated for low power consumption and enhanced stability, is implemented alongside a custom hybrid SRAM-DRAM structure.Using the Cadence Virtuoso platform with the GPDK 45nm process technology, the hybrid SRAM-DRAM architecture demonstrates a significant reduction in power consumption, from 170.15 µW in 6T SRAM to 127.77 µW, highlighting its suitability for low-power applications. These findings establish the hybrid architecture as a promising candidate for next-generation memory systems.

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Low-power high-performance VLSI design
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