A 128Gb/s 0.67pJ/b PAM-4 Transmitter in 18A with RibbonFET and PowerVia
A fully integrated 128Gb/s DAC based transmitter designed for long-reach wireline applications in 18A CMOS process with RibbonFET, PowerVia and backside power delivery network is presented. Design optimization to utilize the lower leakage and faster RibbonFETs for improved energy efficiency and layout techniques to utilize backside power layer for inductor and clock distribution are demonstrated. The TX achieves the best energy efficiency of 0.67pJ/bit (0.75pJ/bit with the PLL) and smallest area reported while meeting key electrical compliance specifications for PAM -4 standards highlighting the continued benefits from CMOS scaling for wire line applications.
Authors
- Rushdy Saba (ORCID: https://orcid.org/0009-0006-3304-4976)
- Frank O’Mahony (ORCID: https://orcid.org/0000-0001-7961-9452)
- Priya Wali (ORCID: https://orcid.org/0000-0002-1996-9319)
- M.C. Clark
- Ajay Balankutty
- Kai Yu (ORCID: https://orcid.org/0000-0002-0938-2987)
- Dong‐Soo Shin (ORCID: https://orcid.org/0000-0002-0863-9138)
- Khoa Nguyen (ORCID: https://orcid.org/0000-0002-7638-6654)
- Sandipan Kundu (ORCID: https://orcid.org/0000-0003-3806-6913)
- Jihwan Kim (ORCID: https://orcid.org/0000-0002-5599-2997)
- Hyunjung Kim (ORCID: https://orcid.org/0000-0003-2115-6891)
- Stephen Kim (ORCID: https://orcid.org/0009-0008-4986-3233)
- Afonso Teles
Institutions
- Intel (United States) (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074855
- Primary Topic
- Photonic and Optical Devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00