Enhancing Power-Performance-Area Scaling of Std-Cell, SRAM, and Analog Designs Through Design-Technology Co-Optimization
This paper shows how advanced semiconductor scaling, constrained by physical and performance limits, continues to achieve Power-Performance-Area (PPA) improvements through Design-Technology Co-Optimization (DTCO). By optimizing process, design (standard cells, SRAM, analog), and product KPIs, next-generation SoCs maintain gains despite shrinking nodes.
Authors
- Hamed Rasouli (ORCID: https://orcid.org/0000-0002-3100-4413)
- Yun Chiang (ORCID: https://orcid.org/0000-0002-2336-4603)
- Changho Jung (ORCID: https://orcid.org/0000-0002-6584-8665)
- Yandong Gao
- Bruce Lim
- P.R. Chidambaram (ORCID: https://orcid.org/0000-0002-7322-2558)
- Giri Nallapati
- Xiaoyong Wang (ORCID: https://orcid.org/0000-0003-1147-0051)
- Hao Wang (ORCID: https://orcid.org/0000-0001-8984-1508)
- Jie Deng (ORCID: https://orcid.org/0000-0003-3632-2266)
- Deepak Sharma (ORCID: https://orcid.org/0000-0003-1415-5735)
- Jun Yuan
- Jason Cheng
- Raghava Denduluri
- Anatoly Kauffman
Institutions
- Qualcomm (United States) (US)
Publication Details
- Published
- 2025-06-08
- DOI
- https://doi.org/10.23919/vlsitechnologyandcir65189.2025.11074818
- Citations
- 1
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.73