First Experimental Demonstration of Dual-Sided N/P FETs in Filp FET (FFET) on 300 mm Wafers for Stacked Transistor Technology in Sub-1nm Nodes

For the first time, dual-sided devices in Flip FET (FEET) were successfully demonstrated on 300 mm wafers, on which the FFET's unique back-to-back stacking of frontside (FS) NFET and backside (BS) PFET were realized. A series of key process modules including wafer bonding, substrate thinning, channel profile optimization, litho overlay correction and BS performance tuning were successfully developed. As a result, FS NFET after flipping behaved well and decent BS PFET (LG of 30 nm, SS of 73.1 mV/dec, DIBL of 24 mV and on-off ratio of 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup>) was achieved, comparable to the FS NFET. Thanks to the separated processes on each side of the wafer, this work further validates the outstanding features of FFET: natural split-gate, good multi- Vr tunablity (~ 500 m V) and better process margin without challenging high aspect ratio vertical patterning as required by CFET. Moreover, dual-sided CMOS was also realized, proving the excellent extendibility of FFET. With the great benefits in process-friendliness, design flexibility and scalability as compared with CFET, FFET is validated to be a crucial candidate for logic nodes beyond 1 nm.