Heterogeneous 3D Integration of Low-Voltage E/D-Mode GaN HEMTs on CMOS Chip for Efficient On-Chip Voltage Regulation in Active Power Delivery Networks

In this work, we present and experimentally demonstrate the heterogeneous 3D integration of low-voltage (LV) E/D-mode GaN power devices on a CMOS chip for a vertically integrated active power delivery network (PDN). Our LV E/D-mode GaN power devices show record-low on-resistance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text {on }}$</tex>) of 2.78/1.85 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Omega \cdot \text{mm}$</tex> and record-high frequency capability (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\mathrm{T}}$</tex>) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$84 / 68 \text{GHz}$</tex> along with breakdown voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\left(V_{\text{BD}}\right)&gt;12 ~\mathrm{V}$</tex> among power devices for active PDN. Furthermore, we innovated by introducing a scaled AlGaN buffer thickness to the direct heat spreading layer, enabling more efficient heat dissipation. This approach reduces thermal resistance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text {TH }}$</tex>) by 13.5 % compared to using only heat-spreading layer bonding techniques.